Fabrication and Optimization of Aggressively Scaled Dual-Bit/Cell Split-Gate Floating-Gate Flash Memory Cell in 55-Nm Node Technology
An aggressively scaled triple self-aligned split-gate floating-gate (FG) NOR-type dual-bit/cell (NORD) flash cell with a common select-gate (SG) was fabricated at 55-nm node technology. Both FG- and SG-length, for the first time, were scaled down to sub-80 nm and sub-60 nm in our NORD flash, respectively. In this paper, performance of aggressively scaled cells were fully characterized by measurements. Firstly, the cell's characteristics were presented by discussing FG- and SG-transistor’s drain-induced barrier lowering (DIBL) effects and SG-FG coupling effect. It was experimentally revealed that excellent immunity of DIBL effect was still obtained in this highly scaled SG-transistor due to the fully isolated SG-channel. Then, optimization from process for FG-transistor has been discussed. It was shown that the properties of subthreshold region of FG-transistor has been improved by introducing dual pockets for half isolated FG-channel. Thirdly, reading biases were also optimized to expand the window of read currents. Finally, a novel cell structure, which is compatible with 55-nm node CMOS technology, was also proposed to further improve the aggressively length-scaled NORD flash cell without sacrificing bit-area
Year of publication: |
[2022]
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Authors: | Chen, Hualun ; Xu, Zhaozhao ; Xiong, Wei ; Zhang, Jian ; Xu, Xiaojun ; Wang, Hui ; Dang, Yang ; Wang, Jinfeng ; Song, Wan ; Tian, Tian ; Liu, Donghua ; Qian, Wensheng ; Kong, Weiran |
Publisher: |
[S.l.] : SSRN |
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