Simulaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities
Year of publication: |
2014
|
---|---|
Authors: | Kim, Seung-kil ; Kim, Jae-gon ; Kim, Hwa-joong |
Published in: |
International journal of production research. - London : Taylor & Francis, ISSN 0020-7543, ZDB-ID 160477-6. - Vol. 52.2014, 12 (15.6.), p. 3710-3724
|
Subject: | order-lot pegging | input release planning | semiconductor wafer fabrication | Lagrangian relaxation | total tardiness | sensitivity analysis |
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